This invention relates to a TFT (thin film transistor) matrix device and a method for fabricating the same, specifically to a TFT matrix device for use in active matrix liquid crystal display devices which control displays by TFTs disposed for the respective picture elements.
Active matrix liquid display devices, along with simple matrix liquid display devices, are used in thin information terminal display devices. An active matrix liquid display device can drive a number of picture elements arranged in a matrix independently from each other.
The active matrix liquid display has an advantage that even if an increase in a number of picture elements accompanies an increase in a line number to be driven, problems, such as drops of duty ratios of drive signals, drops of contrast, decreases of vision angles, etc., do not occur. Accordingly, active matrix liquid crystal devices can provide color displays as good as CRTs (cathode-ray tubes) and has increasing applications as thin flat displays in projection-type televisions, lap-top personal computers.
But a TFT matrix substrate for use in an active matrix liquid crystal display device requires a complicated structure in which TFTs are provided for respective picture elements as the switch devices, which makes fabrication steps of the active matrix liquid display device complicated. A resultant problem is that, in the case that an active matrix liquid crystal display device is large-sized, its fabrication yield much lowers, and its cost rises. In view of this problem, studies are made to simplify structures of active matrix liquid display devices to decrease their fabrication costs.
As screens of active matrix display devices are up-sized, lengths of bus lines for transmitting signals from outside drive circuits are longer, and liquid crystal capacities and parasitic capacities which are loads of the bus lines. Consequently signal delays which are determined by resistances and load capacities of the bus lines are increased, and the signal delays lead to deterioration of display qualities. Thus to suppress drops of the display qualities it is now necessary to decrease resistances of the bus lines and suppress signal delays.
A conventional TFT matrix device will be explained with reference to FIGS. 56 to 60C.
FIG. 56 is a plan view of a conventional TFT matrix device, FIGS. 57A to 58B are sectional views of a TFT region in its fabrication steps, FIG. 59A is a sectional view of the drain bus line region, and FIGS. 60A to 60C are sectional views of a drain bus line region and the picture element electrode region in its fabrication steps.
A plurality of picture element electrode 100 of FIG. 56 are arranged in a matrix. Drain bus lines 101 are provided vertically, and gate bus lines 102 are provided horizontally, as viewed in FIG. 56. A plurality of TFT 103 are positioned near the intersections between the drain bus lines 101 and the gate bus lines 102.
Next, the method of forming each TFT region will be explained in good detail with reference to the sectional view (FIGS. 57A to 58B) along the line X-X' of FIG. 56.
A light shielding film 105 is formed on a glass substrate 106 at a set position, and then an inter-layer insulating film 106 is formed on the entire surface of the glass substrate 106. The glass substrate 104 with the inter-layer insulating film 106 thereon will be hereinafter called transparent insulating substrate 107.
Then, a transparent conductor film of, e.g., ITO (Indium Tin Oxide) film is formed on the transparent insulating substrate 107, and then an impurity-content amorphous silicon film is formed on the transparent conductor film.
Subsequently, the impurity-content amorphous silicon film and the transparent conductor film are patterned to form a source electrode 108S and a drain electrode 108D of the transparent conductor film, and a source electrode contact layer 109S and a drain electrode contact layer 109D of the impurity-content amorphous silicon film. A region between the edges of the source electrode 108 and the drain electrode 108D, which are opposed to each other above the light shielding film 105, will be a channel region of TFT to be formed (FIG. 57A).
Then, on the entire surface are formed an amorphous silicon film 110a, a SiN (silicon nitride) film 111a, and an Al (aluminum) film 112a in this stated order, and then a resist film 113 is deposited on the Al film 112a. The resist film 113 is patterned in a set configuration (FIG. 57B).
Subsequently, with the patterned resist film 113 as the mask, an Al film 112a, an SiN film 111a, an amorphous silicon film 110a, a source electrode contact layer 109S and a drain electrode contact layer 109D are etched into a mesa to form a gate electrode 112 of the Al film 112a, a gate insulating film 111 of the SiN film 111a, and an active layer, or an operational semiconductor layer 110 of the amorphous silicon film 110a (FIG. 58A).
Thus is fabricated a staggered TFT including the source electrode 108S and the drain electrode 108D formed opposed to each other on the transparent insulating substrate 107, the operational semiconductor layer 110 connected to the source electrode 108S and the drain electrode 108D respectively through the source electrode contact layer 109S and the drain electrode contact layer 109D, and the gate electrode 112 formed on the channel region of the operational semiconductor layer 110 between the source electrode 108S and the drain electrode 108D through the gate insulating film 111 (FIG. 58B).
In the thus-fabricated staggered TFT 102, as apparent in FIG. 58B, the side surfaces of the gate electrode 112, those of the gate insulating film 111, those of the operational semiconductor layer 110, and those of the source electrode contact layer 109S or the drain electrode contact layer 109D are in the same plane. Accordingly, there is a possibility that leak currents might flow through the side surfaces between the gate electrode 112 and the source electrode 108S or the drain electrode 108D.
Next, the method for forming the drain bus line region will be explained in good detail with reference to a sectional view (FIG. 59A) along the line Y-Y' in FIG. 56.
This forming method is involved in the simple method for fabricating a TFT matrix device disclosed in Japanese Patent Laid-Open Publication No. 501562/1984, Japanese Patent Laid-Open Publication No. 500745/1987, etc.
The source electrode 108S and the drain electrode 108D of the transparent conductor film, the drain bus line 101, and the picture element electrode 100 are patterned on the transparent insulating substrate 107 using a first mask, and then on the entire surface the amorphous silicon film 110a, the SiN film 111a, and the Al film 112a are formed in the stated order. The impurity-content amorphous silicon film forming the source electrode contact layer and the drain electrode contact layer are not explained here.
Subsequently, using a second mask, the Al film 112a, the SiN film 111a and the amorphous silicon film 110a are etched off to pattern the gate bus line 102 serving also as the gate electrode 112 of the Al film 112a, and separate the TFT 103. Thus as shown in FIG. 57A, the drain bus line 101 is formed of the transparent conductor film as the picture element electrode 100.
Thus, because the drain bus line 101 is formed of the transparent conductor film having a higher specific resistance compared with a metal film, the drain bus line 101 has high resistances. When a film thickness of the transparent conductor film is increased for lower resistances, the coverage of the operational conductor layer 110 formed on the transparent conductor film is lowered, which affects on characteristics of the TFT 103. As a result, a thickness of the transparent conductor film is limited to about 200 nm, and the drain bus line 101 cannot help having a high resistance.
As means against high resistances of the drain bus line 101 sometimes the drain bus line as in FIG. 57B is used.
In this case, the electrode layer patterned using the first mask is provided by a superposed layers comprising the transparent conductor film and the metal film 114. In the same way as FIG. 57A, the gate bus line 102 functioning as the gate electrode 112 is patterned using the second mask, and the SiN film 111a and the amorphous silicon film 110a are etched to separate the TFT 103. Then that part of the metal film 114 on the picture element electrode 100 is etched to make the picture element electrode region transparent.
That is, for a lower resistance of the drain bus line, that of the Al film 112a in a region 115 on the drain bus line 101 between two adjacent gate bus lines 102 is left, whereby the metal film 114 below the Al film 112a at the region 115 is left.
Thus, the drain bus line 101 has a superposed layer structure comprising the transparent conductor film and the metal film 114 thereon in the region 115 between intersections of the drain bus line 101 with the adjacent gate bus lines 102, and in regions 116 at these intersections. In this means, the drain bus line has lower resistance values than in the conventional art of FIG. 57A.
But, when the Al film 112a left in the region 115 on the drain bus line 101 is electrically connected to at least one gate bus line 102, a capacity coupling between the bus lines is increased, resultantly causing problems of deformations in a drive waveform, and short circuits between the bus lines. So that, it is necessary to provide regions 117, 118 without the Al film 112a left between the region 115 on the drain bs line 101 and the gate bus line 102.
In the presence of the regions 117, 118 without the Al film 112a left, those parts of the metal film 114 on the transparent conductor film are concurrently etched off in the step of etching off that part of the metal film 114 on the picture element electrode 100 to make the picture element electrode region transparent. As shown in FIG. 59B, the drain bus line 101 includes only the transparent conductor film alone in the regions 117, 118, so that increases of a resistance value of the drain bus line 101 due to a resistance of the transparent conductor film in these regions 117, 118 cannot be prevented.
Thus, in either case of FIGS. 59A and 59B, the drain bus lines 101 cannot be prevented from having high resistance values.
Next, the method for forming the drain bus line region and the picture element electrode regions will be explained in good detail with reference to the sectional view (FIGS. 60A to 60C) along the line Z-Z' in FIG. 56.
A TFT matrix device usually includes transparent picture element electrode regions for bright displays, and drain bus line regions for low resistances. For this reason, the picture element electrodes are formed of a transparent conductor film, and the drain bus lines are formed of a transparent conductor film with a metal film thereon.
First, a transparent conductor film is formed on the entire surface of a transparent conductor substrate 107, and a first resist film 119 is patterned in a set configuration. Subsequently, with the first resist film 119 as the mask, the transparent conductor film is etched to form picture element electrodes 100 and drain bus lines 101 (FIG. 60A).
Then, a metal film 120 is formed on the entire surface (FIG. 60B). Subsequently, a second resist film 121 is patterned in a configuration of the drain bus lines on the metal film 120. Then with the second resist film 121 as the mask, the metal film 120 on the picture element electrodes 100 is etched off (FIG. 60C).
Thus, the picture element electrodes 100 are formed of the transparent conductor film alone, whereby transparency of the picture element electrode region is ensured, while the metal film 120 is formed on the drain bus lines 101, whereby the drain bus lines 101 having the same structure as in FIG. 59B are formed, and their resistance value is decreased.
But in the conventional method of FIGS. 60A to 60C, the picture element electrodes 100 and the drain bus lines 101 are formed by two lithography steps using the two different resist films 119, 121. For this reason, a design has to be made, taking into consideration an alignment margin between the first and the second resist films 119, 121, and a larger area is required for the bus lines with a resultant problem of decreased opening ratios.
As described above, the conventional TFT matrix device has a problem that leak currents flow between the gate electrode 112 and the source electrode 108S or the drain electrode 108D along the side surfaces of the gate electrodes 112, the gate insulating film 111 and the operational semiconductor layer 110, and the source electrode contact layer 109S or the drain electrode contact layer 109D, which are in one plane as shown in FIG. 58B.
Another problem is that, as in FIGS. 59A and 59B, the drain bus lines 101 cannot be prevented from having high resistances.
Further another problem is that, as in FIGS. 60A to 60C, in the case that transparency of the picture element electrodes 100 is ensured, and a resistance of the drain bus line 101 is decreased, a larger area is needed to form the drain bus line 166, intruding an area of the picture element electrodes 100 with a result of decreased opening ratios.